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CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9
Integrated Device Technology, Inc.
IDT7200L IDT7201LA IDT7202LA
FEATURES:
* * * * * First-In/First-Out dual-port memory 256 x 9 organization (IDT7200) 512 x 9 organization (IDT7201) 1K x 9 organization (IDT7202) Low power consumption -- Active: 770mW (max.) --Power-down: 2.75mW (max.) Ultra high speed--12ns access time Asynchronous and simultaneous read and write Fully expandable by both word depth and/or bit width Pin and functionally compatible with 720X family Status Flags: Empty, Half-Full, Full Auto-retransmit capability High-performance CEMOSTM technology Military product compliant to MIL-STD-883, Class B Standard Military Drawing #5962-87531, 5962-89666, 5962-89863 and 5962-89536 are listed on this function Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load and empty data on a first-in/first-out basis. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. It also features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed low to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. The IDT7200/7201/7202 are fabricated using IDT's highspeed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/ writes in multiprocessing and rate buffer applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.
* * * * * * * * * *
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS (D 0 -D8)
W
WRITE CONTROL
WRITE POINTER
RAM ARRAY 256 x 9 512 x 9 1024 x 9
READ POINTER
R
READ CONTROL
THREESTATE BUFFERS DATA OUTPUTS (Q 0 -Q8)
RS
RESET LOGIC
FLAG LOGIC
EF FF XO/HF
FL/RT
XI
EXPANSION LOGIC
2679 drw 01
The IDT logo is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2679/7
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
D3 D8
W
D8 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 P28-1, P28-2, D28-1, D28-3, E28-2, SO28-3
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7
432 D2 D1 D0 5 6 7 8 9 10 11 12 13
1
32 31 30 29 28 27 26 25 24 23 22 21 D6 D7 NC
XI FF
Q0 Q1 Q2 Q3 Q8 GND
FL/RT RS EF XO/HF
Q7 Q6 Q5 Q4
XI FF
Q0 Q1 NC Q2
D5
W
PIN CONFIGURATIONS
INDEX
NC VCC D4
J32-1 & L32-1
FL/RT RS EF XO/HF
Q7 Q6
14 15 16 17 18 19 20
GND NC
R
2679 drw 02a
Q3 Q8
R
Q4
Q5
2679 drw 02b
DIP/SOIC/CERPACK TOP VIEW
NOTE: 1. CERPACK (E28-2) and 600-mil-wide DIP (P28-1 and D28-1) not available for 7200.
LCC/PLCC TOP VIEW
NOTE: 1. LCC (L32-1) not available for 7200.
ABSOLUTE MAXIMUM RATINGS
Symbol Rating VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature IOUT DC Output Current
(1)
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCCM VCCC GND VIH(1) VIH(1) Parameter Military Supply Voltage Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input High Voltage Mlitary Input Low Voltage Commercial and Military Min. 4.5 4.5 0 2.0 2.2 -- Typ. 5.0 5.0 0 -- -- -- Max. 5.5 5.5 0 -- -- 0.8 Unit V V V V V V
Com'l. Mil. Unit -0.5 to +7.0 -0.5 to +7.0 V
0 to +70
-55 to +125
C C C mA
-55 to +125 -65 to +135 -55 to +125 -65 to +155 50 50
VIL(2)
NOTE: 2679 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty.
NOTE: 1. VIH = 2.6V for XI input (commercial). VIH = 2.8V for XI input (military). 2. 1.5V undershoots are allowed for 10ns once per cycle.
2679 tbl 03
CAPACITANCE (TA = +25C, f = 1.0 MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Condition VIN = 0V VOUT = 0V Max. 8 8 Unit pF pF
2679 tbl 02
NOTE: 1. This parameter is sampled and not 100% tested.
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5.0V10%, TA = -55C to +125C)
IDT7200L IDT7201LA IDT7202LA Commercial tA = 12, 15, 20 ns Symbol ILI(1) ILO
(2)
IDT7200L IDT7201LA IDT7202LA Military tA = 20 ns Min. -10 -10 2.4 -- -- -- -- Typ. -- -- -- -- -- -- -- Max. 10 10 -- 0.4 140
(4)
IDT7200L IDT7201LA IDT7202LA Commercial tA = 25, 35 ns Min. -1 -10 2.4 -- -- -- -- Typ. Max. Unit -- -- -- -- -- -- -- 1 10 -- 0.4 125
(4)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage IOH = -2mA Output Logic "0" Voltage IOL = 8mA Active Power Supply Current Standby Current (R=W=RS=FL/RT=VIH) Power Down Current (All Input = VCC - 0.2V)
Min. -1 -10 2.4 -- -- -- --
Typ. -- -- -- -- -- -- --
Max. 1 10 -- 0.4 125
(4)
A A V V mA mA mA
05 2679 tbl 04
VOH VOL ICC1
(3)
ICC2(3) ICC3(L)(3)
15 0.5
20 0.9
15 0.5
NOTES: 1. Measurements with 0.4 VIN VCC. 2. R VIH, 0.4 VOUT VCC. 3. ICC measurements are made with outputs open (only capacitive loading). 4. Tested at f = 20MHz.
DC ELECTRICAL CHARACTERISTICS (Continued)
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5.0V10%, TA = -55C to +125C)
IDT7200L IDT7201LA IDT7202LA Military tA = 30, 40 ns Symbol ILI
(1)
IDT7200L IDT7201LA IDT7202LA Commercial tA = 50 ns Min. -1 -10 2.4 -- -- -- -- Typ. Max. -- -- -- -- 50 5 -- 1 10 -- 0.4 80 8 0.5
IDT7200L IDT7201LA IDT7202LA Military tA = 50, 65, 80, 120 ns Min. -10 -10 2.4 -- -- -- -- Typ. -- -- -- -- 70 8 -- Max. Unit 10 10 -- 0.4 100 15 0.9 A A V V mA mA mA
2679 tbl 05
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage IOH = -2mA Output Logic "0" Voltage IOL = 8mA Active Power Supply Current Standby Current (R=W=RS=FL/RT=VIH) Power Down Current (All Input = VCC - 0.2V)
Min. -10 -10 2.4 -- -- -- --
Typ. -- -- -- -- -- -- --
Max. 10 10 -- 0.4 140
(4)
ILO(2) VOH VOL ICC1 ICC2
(3) (3)
20 0.9
ICC3(L)(3)
NOTES: 1. Measurements with 0.4 VIN VCC. 2. R VIH, 0.4 VOUT VCC. 3. ICC measurements are made with outputs open (only capacitive loading). 4. Tested at f = 20MHz.
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5.0V10%, TA = -55C to +125C)
Commercial 7200L12 7200L15 7201LA12 7201LA15 7202LA12 7202LA15 Symbol Parameter tS tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSS tRSR tRTC tRT tRTS tRTR tEFL tRTF tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tXOL tXOH tXI tXIR tXIS Shift Frequency Read Cycle Time Access Time Read Recovery Time Read Pulse Width
(2)
Com'l & Mil. 7200L20 7201LA20 7202LA20 -- 30 -- 10 20 5 5 5 -- 30 20 10 12 0 30 20 20 10 30 20 20 10 -- -- -- -- -- 20 -- -- -- -- 20 -- -- 20 10 10 33.3 -- 20 -- -- -- -- -- 15 -- -- -- -- -- -- -- -- -- -- -- -- -- 30 30 30 20 20 -- 20 20 30 30 -- 20 20 -- -- --
Com'l
Military
Com'l 7200L35 7201LA35 7202LA35 -- 45 -- 10 35 5 10 5 -- 45 35 10 18 0 45 35 35 10 45 35 35 10 -- -- -- -- -- 35 -- -- -- -- 35 -- -- 35 10 10 22.2 MHz -- 35 -- -- -- -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- -- 45 45 45 30 30 -- 30 30 45 45 -- 35 35 -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2679 tbl 06
7200L25 7200L30 7201LA25 7201LA30 7202LA25 7202LA30 -- 35 -- 10 25 5 5 5 -- 35 25 10 15 0 35 25 25 10 35 25 25 10 -- -- -- -- -- 25 -- -- -- -- 25 -- -- 25 10 10 28.5 -- 25 -- -- -- -- -- 18 -- -- -- -- -- -- -- -- -- -- -- -- -- 35 35 35 25 25 -- 25 25 35 35 -- 25 25 -- -- -- -- 40 -- 10 30 5 5 5 -- 40 30 10 18 0 40 30 30 10 40 30 30 10 -- -- -- -- -- 30 -- -- -- -- 30 -- -- 30 10 10 25 -- 30 -- -- -- -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- -- 40 40 40 30 30 -- 30 30 40 40 -- 30 30 -- -- --
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit -- 20 -- 8 12 3 3 5 -- 20 12 8 9 0 20
(2) (3, 4)
50 -- 12 -- -- -- -- -- 12 -- -- -- -- -- -- -- -- -- -- -- -- -- 12 17 20 12 14 -- 12 14 17 17 -- 12 12 -- -- --
-- 25 -- 10 15 5 5 5 -- 25 15 10 11 0 25 15 15 10 25 15 15 10 -- -- -- -- -- 15 -- -- -- -- 15 -- -- 15 10 10
40 -- 15 -- -- -- -- -- 15 -- -- -- -- -- -- -- -- -- -- -- -- -- 25 25 25 15 15 -- 15 15 25 25 -- 15 15 -- -- --
Read Pulse Low to Data Bus at Low Z(3) Write Pulse High to Data Bus at Low Z Data Valid from Read Pulse High Read Pulse High to Data Bus at High Z(3) Write Cycle Time Write Pulse Width(2) Write Recovery Time Data Set-up Time Data Hold Time Reset Cycle Time Reset Pulse Width Reset Set-up Time(3) Reset Recovery Time Retransmit Cycle Time Retransmit Pulse Width
(2) (3)
12 12 8 20 12 12 8 -- -- -- -- -- 12 -- -- -- -- 12 -- -- 12 8 8
Retransmit Set-up Time
Retransmit Recovery Time Reset to Empty Flag Low Retransmit Low to Flags Valid Read Low to Empty Flag Low Read High to Full Flag High Read Pulse Width after EF High Write High to Empty Flag High Write Low to Full Flag Low Write Low to Half-Full Flag Low Read High to Half-Full Flag High Write Pulse Width after FF High Read/Write to XO Low Read/Write to XO High
tHFH,FFH Reset to Half-Full and Full Flag High
XI Pulse Width(2) XI Recovery Time XI Set-up Time
NOTES: 1. Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode.
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) (Continued)
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5.0V10%, TA = -55C to +125C)
Military 7200 L40 7201LA40 7202LA40 Symbol tS tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSS tRSR tRTC tRT tRTS tRTR tEFL tRTF tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tXOL tXOH tXI tXIR tXIS Parameter Shift Frequency Read Cycle Time Access Time Read Recovery Time Read Pulse Width
(3) (4)
Com'l & Mil. 7200L50 7201LA50 7202LA50 Max. 15 -- 50 -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- -- -- -- -- 65 65 65 45 45 -- 45 45 65 65 -- 50 50 -- -- -- -- 65 -- 15 50 10 15 5 -- 65 50 15 30 5 65 50 50 15 65 50 50 15 -- -- -- -- -- 50 -- -- -- -- 50 -- -- 50 10 15 7200L65 7201LA65 7202LA65 Min. -- 80 -- 15 65 10 15 5 -- 80 65 15 30 10 80 65 65 15 80 65 65 15 -- -- -- -- -- 65 -- -- -- -- 65 -- -- 65 10 15 Max. 12.5 -- 65 -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- -- -- -- -- 80 80 80 60 60 -- 60 60 80 80 -- 65 65 -- -- --
Military(2) 7200L80 7201LA80 7202LA80 Min. -- 100 -- 20 80 10 20 5 -- 100 80 20 40 10 100 80 80 20 100 80 80 20 -- -- -- -- -- 80 -- -- -- -- 80 -- -- 80 10 15 Max. 10 -- 80 -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- -- -- -- -- 100 100 100 60 60 -- 60 60 100 100 -- 80 80 -- -- -- 7200L120 7201LA120 7202LA120 Min. -- 140 -- 20 120 10 20 5 -- 140 120 20 40 10 140 120 120 20 140 120 120 20 -- -- -- -- -- 120 -- -- -- -- 120 -- -- 120 10 15 Max. 7 -- 120 -- -- -- -- -- 35 -- -- -- -- -- -- -- -- -- -- -- -- -- 140 140 140 60 60 -- 60 60 140 140 -- 120 120 -- -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2679 tbl 07
Min. -- 50 -- 10 40 5 10 5
(4)
Max. Min. 20 -- 40 -- -- -- -- -- 25 -- -- -- -- -- -- -- -- -- -- -- -- -- 50 50 50 30 35 -- 35 35 50 50 -- 40 40 -- -- --
Read Pulse Low to Data Bus at Low Z Data Valid from Read Pulse High
Write Pulse High to Data Bus at Low Z(4, 5) Read Pulse High to Data Bus at High Z Write Cycle Time Write Pulse Width(3) Write Recovery Time Data Set-up Time Data Hold Time Reset Cycle Time Reset Pulse Width(3) Reset Set-up Time
(4)
-- 50 40 10 20 0 50 40 40 10 50
Reset Recovery Time Retransmit Cycle Time Retransmit Pulse Width
(3)
40 40 10 -- -- -- -- -- 40 -- -- -- -- 40 -- -- 40 10 10
Retransmit Set-up Time(4) Retransmit Recovery Time Reset to Empty Flag Low Retransmit Low to Flags Valid Read Low to Empty Flag Low Read High to Full Flag High Read Pulse Width after EF High Write High to Empty Flag High Write Low to Full Flag Low Write Low to Half-Full Flag Low Read High to Half-Full Flag High Write Pulse Width after FF High Read/Write to XO Low Read/Write to XO High
tHFH,FFH Reset to Half-Full and Full Flag High
XI Pulse Width XI Recovery Time XI Set-up Time
(3)
NOTES: 1. Timings referenced as in AC Test Conditions 2. Speed grades 65, 80 and 120 not available in the CERPACK 3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode.
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure 1
2679 tbl 08
5V
1.1K TO OUTPUT PIN 680
30pF*
2679 drw 03
or equivalent circuit Figure 1. Output Load * Includes scope and jig capacitances.
SIGNAL DESCRIPTIONS INPUTS:
DATA IN (D0 - D8) Data inputs for 9-bit wide data.
CONTROLS: RESET (RS RS)
Reset is accomplished whenever the Reset (RS) input is taken to a low state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in R W the high state during the window shown in Figure 2, (i.e., tRSS before the rising edge of RS and should not change RS) until tRSR after the rising edge of RS Half-Full Flag (HF RS. HF) will be reset to high after Reset (RS RS). WRITE ENABLE (W) W A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go high after tRFF, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. READ ENABLE (R) R A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes high,
the Data Outputs (Q0 - Q8) will return to a high impedance condition until the next Read operation. When all data has been read from the FIFO, the Empty Flag (EF) will go low, allowing the "final" read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go high after tWEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes in R will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FL RT) FL/RT This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the restransmit input. The Single Device Mode is initiated by grounding the Expansion In (XI). The IDT7200/7201A/7202A can be made to retransmit data when the Retransmit Enable control (RT) input is pulsed low. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the high state during retransmit. This feature is useful when less than 256/ 512/1024 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. EXPANSION IN (XI XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode.
OUTPUTS:
FULL FLAG (FF FF) The Full Flag (FF) will go low, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go low after 256 writes for IDT7200, 512 writes for the IDT7201A and 1024 writes for the IDT7202A.
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
EMPTY FLAG (EF EF) The Empty Flag (EF) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO HF) XO/HF This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by using rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. DATA OUTPUTS (Q0 - Q8) Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a high state.
t RSC t RS RS t RSS W t RSS R t EFL EF t HFH , t FFH HF, FF
2679 drw 04
t RSR
Figure 2. Reset NOTES: 1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS.
t RC t RR tA R t RLZ Q0 - Q8 t WPW W tDS D0 - D8 tDH t DV DATA OUT VALID t WC t WR tA
t RPW
t RHZ DATA OUT VALID
DATA IN VALID
DATA IN VALID
2679 drw 05
Figure 3. Asynchronous Write and Read Operation
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LAST WRITE R
IGNORED WRITE
FIRST READ
ADDITIONAL READS
FIRST WRITE
W t WFF FF
2679 drw 06
tRFF
Figure 4. Full Flag From Last Write to First Read
LAST READ W
IGNORED READ
FIRST WRITE
ADDITIONAL WRITES
FIRST READ
R t REF EF tA DATA OUT VALID VALID
2679 drw 07
tWEF
Figure 5. Empty Flag From Last Read to First Write
t RTC t RT RT t RTS W,R
RTF
t RTR
HF, EF, FF
FLAG VALID
2679 drw 08
Figure 6. Retransmit
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W t WEF EF t RPE R
2679 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
R t RFF FF t WPF W
2679 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse
W
t
RHF
R
HALF-FULL OR LESS
t
WHF MORE THAN HALF-FULL HALF-FULL OR LESS 2678 drw 11
HF
Figure 9. Half-Full Flag Timing
WRITE TO LAST PHYSICAL LOCATION
W R t XOL XO t XOH
READ FROM LAST PHYSICAL LOCATION
t XOL
t XOH
2679 drw 12
Figure 10. Expansion Out
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t XI XI t XIS W
WRITE TO FIRST PHYSICAL LOCATION
t XIR
t XIS R
Figure 11. Expansion In
READ FROM FIRST PHYSICAL LOCATION
2679 drw 13
OPERATING MODES:
Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. Single Device Mode A single IDT7200/7201A/7202A may be used when the application requirements are for 256/512/1024 words or less. The IDT7200/7201A/7202A is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 12). Depth Expansion The IDT7200/7201A/7202A can easily be adapted to applications when the requirements are for greater than 256/512/ 1024 words. Figure 14 demonstrates Depth Expansion using three IDT7200/7201A/7202As. Any depth can be attained by adding additional IDT7200/7201A/7202As. The IDT7200/ 7201A/7202A operates in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the high state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 14. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 14. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO Modules.
USAGE MODES:
Width Expansion Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any one device. Figure 13 demonstrates an 18-bit word width by using two IDT7200/7201A/7202As. Any word width can be attained by adding additional IDT7200/7201A/7202As (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT7200/7201A/7202As as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of W, called the first write edge, and it remains on the bus until the R line is raised from low-to-high, after which the bus would go into a three-state mode after tRHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line being low causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15).
5.03
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(HALF-FULL FLAG) WRITE (W) 9 DATA IN (D) FULL FLAG (FF) RESET (RS)
(HF) READ (R) IDT 7200/ 7201A/ 7202A 9 DATA OUT (Q) EMPTY FLAG (EF) RETRANSMIT (RT)
EXPANSION IN (XI)
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Figure 12. Block Diagram of Single 256/512/1024 x 9 FIFO
HF
18 DATA IN (D) WRITE (W) FULL FLAG (FF) RESET (RS) 9 IDT 7200/ 7201A/ 7202A 9 9
HF
IDT 7200/ 7201A/ 7202A 9
READ (R) EMPTY FLAG (EF) RETRANSMIT (RT)
XI
XI
18 DATA OUT (Q)
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Figure 13. Block Diagram of 256/512/1024 x 18 FIFO Memory Used in Width Expansion Mode
TABLE I--RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs Mode Reset Retransmit Read/Write
RS
0 1 1
RT
X 0 1
XI
0 0 0
Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Unchanged Increment(1) Increment(1)
Outputs
EF
0 X X
FF
1 X X
HF
1 X X
2679 tbl 09
NOTE: 1. Pointer will increment if flag is High.
TABLE II--RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs Mode Reset First Device Reset All Other Devices Read/Write
RS
0 0 1
FL
0 1 X
XI
(1) (1) (1)
Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Location Zero X X
Outputs
EF
0 0 X
FF
1 1 X
2679 tbl 10
NOTE: 1. XI is connected to XO of previous device. See Figure 14. XI = Expansion Input, HF = Half-Full Flag Output
RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output,
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11
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
XO W
D 9
FF
9
IDT 7200/ 7201A/ 7202A
EF
9
R
Q VCC
FL
XI XO FULL
9
FF
IDT 7200/ 7201A/ 7202A
EF FL
EMPTY
XI XO FF
9 IDT 7200/ 7201A/ 7202A
EF
RS
XI
FL
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Figure 14. Block Diagram of 768 x 9/1536 x 9/3072 x 9 FIFO Memory (Depth Expansion)
Q 0 -Q 8 Q 0 -Q 8 IDT7200/ IDT7201A/ IDT7202A DEPTH EXPANSION BLOCK D 0 -D 8 D 0 -D N D9 -D N
Q 9 -Q 17 *** Q 9 -Q 17 IDT7200/ IDT7201A/ IDT7202A DEPTH EXPANSION BLOCK D 9 -D 17 *** D 18 -D N D(N-8)-DN
Q (N-8) -Q N Q (N-8) -Q N IDT7200/ IDT7201A/ IDT7202A DEPTH EXPANSION BLOCK D (N-8)-D N
R, W, RS
***
2679 drw 17
Figure 15. Compound FIFO Expansion NOTES: 1. For depth expsansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13.
5.03
12
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WA FFA
DA 0-8
IDT 7200/ IDT 7201A/ 7201A 7202A
RB EFB HF B
QB 0-8
SYSTEM A
SYSTEM B
QA 0-8
DB 0-8
IDT 7200/ 7201A/ 7202A
RA HFA EF A
WB FFB
2679 drw 18
Figure 16. Bidirectional FIFO Mode
DATA IN
W t RPE R
EF t REF t WEF t WLZ DATA OUT tA DATA OUT VALID
2679 drw 19
Figure 17. Read Data Flow-Through Mode
R t WPF W t RFF FF t WFF DATA IN VALID t DS tA DATA OUT DATAOUT VALID
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t DH
DATAIN
Figure 18. Write Data Flow-Through Mode
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXX Device Type X Power XXX Speed X Package X Process/ Temperature Range Blank B Commercial (0C to + 70C) Military (-55C to + 125C) Compliant to MIL-STD-883, Class B
P TP D TD J SO L XE
Plastic DIP (7201 & 7202 Only) Plastic THINDIP CERDIP (7201 & 7202 Only) Ceramic THINDIP Plastic Leaded Chip Carrier SOIC Leadless Chip Carrier (7201 & 7202 Only) CERPACK (7201 & 7202 Only)
12 15 20 25 30 35 40 50 65 80 120 LA
Commerical Only Commercial Only Commercial Only Military Only Commercial Only Military Only Military only-except XE package Low Power*
Access Time (tA) Speed in Nanoseconds
7200 7201 7202
* "A" to be included for 7201 and 7202 ordering part number.
256 x 9-Bit FIFO 512 x 9-Bit FIFO 1024 x 9-Bit FIFO
2679 drw 21
5.03
14

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